1. Field of the Invention
The present invention relates to drivers and, more particularly, to a driver with a bulk switching MOS power transistor.
2. Description of the Related Art
A MOS transistor is a well-known circuit device that controllably varies the current that flows between a source region and a drain region. A MOS power transistor is a larger MOS transistor that is capable of handling much larger magnitudes of current. A driver is another well-known circuit device that utilizes a PMOS power transistor and an NMOS power transistor.
The PMOS transistor has a source connected to a voltage source, and a drain connected to an output node. In addition, the PMOS transistor has a gate, and an n-bulk that is connected to the voltage source. The NMOS transistor has a source connected to ground, and a drain connected to the output node. Further, the NMOS transistor has a gate, and a p-bulk that is connected to ground.
In operation, when an input signal transitions from a logic low to a logic high, the PMOS transistor turns off and the NMOS transistor turns on. As a result, the NMOS transistor pulls the output node to ground. On the other hand, when the input signal transitions from a logic high to a logic low, the NMOS transistor turns off and the PMOS transistor turns on. As a result, the PMOS transistor pulls the output node up to approximately the voltage source.
One of the advantages of the above-described driver is that only one transistor is on when the input logic state is either a logic high or a logic low. To minimize leakage current when the PMOS and NMOS transistors are turned off, the n-bulk and p-bulk, respectively, are held at the voltage source and ground, respectively.
The present invention provides a driver with a bulk switching MOS power transistor. A driver in accordance with the present invention includes a p-channel MOS transistor that has a p+ source connected to a supply voltage, a p+ drain connected to a first node, a gate, and an n-bulk connected to a second node.
In addition, the driver further includes an n-channel MOS transistor that has an n+ source connected to ground, an n+ drain connected to the first node, a gate, and a p-bulk connected to a p-bulk voltage. Further, the driver includes a gate signal generator that outputs a PMOS gate signal to the gate of the p-channel MOS transistor, an NMOS gate signal to the gate of the n-channel MOS transistor, and a control signal. The PMOS and NMOS gate signals are non-overlapping.
The driver also includes a first switch that is connected to ground, the control signal, and the n-bulk of the p-channel MOS transistor via the second node. The driver additionally includes a second switch connected to ground and the control signal, and a resistor that is connected to the n-bulk of the p-channel MOS transistor. A current flows through the resistor to ground when the second switch is closed, and does not flow through the resistor when the second switch is open.
The present invention also includes a method of driving a signal with the driver. The method includes the steps of turning off the n-channel MOS transistor, turning on the p-channel MOS transistor after the n-channel MOS transistor has been turned off, and connecting the n-bulk to ground via the resistor when the p-channel MOS transistor is on.
The method can also include the steps of turning off the p-channel MOS transistor, connecting the n-bulk to a voltage greater than ground when the p-channel transistor is off, and turning on the n-channel MOS transistor.
The present invention also includes a MOS transistor that includes a plurality of first strips of a first conductivity type. A first strip has a width that varies with length from a first width to a second larger width to the first width. The MOS transistor also includes a plurality of second strips of the first conductivity type. A second strip has a width that varies with length from a third width to a fourth smaller width to the third width. A line normal to the lengths of the first strip and the second strip passes through the first width and the third width. The third width is larger than the first width.
The MOS transistor additionally includes a plurality of channel region strips. A channel region strip is located between adjacent first and second strips. The channel region strip has a shape that varies with length. The shape is defined by the adjacent first and second strips. Further, the MOS transistor includes a plurality of gate strips. A gate strip is formed over each channel region strip. The gate strip has a shape that varies with length and substantially matches the shape of the channel region strip.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.